This invention relates to operational amplifiers, and more particularly to dual-mode multiple stage operational amplifiers.
Two-stage CMOS operational amplifiers are advantageous in many circuits because they are able to provide a large transconductance, a fast settling time and sufficiently high gain.
Two-stage operational amplifier techniques are well known. Certain common two-stage operational amplifiers include compensation components, such as, for example, a nulling resistor, and/or pole-splitting capacitor, configured to generate a zero and separate a dominant pole and a second order pole.
Compensating a two-stage operational amplifier presents a challenge in a CMOS process that does not include a capacitor layer. One area-effective way to create a capacitor, is to utilize the gate capacitance of a MOSFET device with a formed channel. To keep the compensation capacitor turned on, however, the voltage difference between the two operational amplifier stages needs to be larger than the MOSFET threshold voltage under all of the process, supply, and temperature conditions. Such a solution may not be suitable for certain devices.
Thus, there is a continuing need for improved operational amplifiers that are suitable for implementation in a CMOS integrated circuitry and perhaps other types of circuitry.